The emergence of the cloud for computing applications has increased the demand for off-site installations, known as data centers, that store data and run applications accessed by remotely connected computer device users. Such data centers typically have massive numbers of servers, switches, and storage devices to store and manage data. A typical data center has physical rack structures with attendant power and communication connections. The racks are arranged in rows throughout the room, or rooms, of the data center. Each rack may hold multiple network devices such as servers, switches, and storage devices. As different functions are requested by operators of data centers, specialized servers are required. Such specialized servers may include a storage server, a computing server, a graphic processing unit server, or a network switch server. Each type of server requires different setups of hardware and software.
Thus, hardware design of basic platforms for servers, such as a baseboard, usually requires consideration of a variety of uses and subsumes most server functions throughout. A baseboard is a circuit board that includes a baseboard management controller and components to support a variety of specialized mainboards with different functions. Such a server platform typically supports the best compatibility for different server deployment scenarios. Hence optimal hardware design of server platforms may contain multiplexer and data selector circuits on the server baseboard, to allow selection of different functions on specialized boards. Such circuits accommodate maximum variables and independent requirements. The designs use informal logic programming and controllers to select the correct circuit to fulfill each complete function. These variables and independent requirements are usually exclusively present and permanently enabled or disabled on a server. However, server platforms are not generally designed to allow modifications after a server has been shipped to a customer.
Recently, adaptable server platforms have been introduced that allow a customer to customize functions. Such adaptable server platforms may derive their adaptability from either the physical hardware component as a connector, a memory socket, or an IO peripheral slot, which can adopt more devices. Such platforms may also include options for a specific server function, which can be activated by sensing the setting of logic programming and a controller. Such mechanisms bring a flexible usage model to such adaptable server designs.
In order to achieve flexibility without increasing cost, the baseboard design of a server may reserve replaceable, added, and removable hardware circuits. Once a server design is scheduled for mass production, it may still have a variety of uses available to a customer. In such cases, the factory site may use a customer manifest to correctly build the desired functionality into a server by using the same baseboard design, but adjusting the settings of logic programming and the controller to configure the baseboard. Thus, factory production lines must have the provision of logic programming and controller configurations relying on the traditional Basic Input Output System (BIOS) and a baseboard management controller (BMC). These components are the principal firmware that are programed with the initial associated hardware configuration for the server. This saves time and money on production lines for designing, replacing and preparing different motherboards for different servers.
In general, setting logic programming and configuring a controller are based on fixed parameters of firmware and a static state of hardware signals. The fixed parameter could be a partition of a combination firmware image file which is built by the firmware designer of the baseboard. Such parameters may be stored in the non-volatile memory of the baseboard such as a Serial Peripheral Interface (SPI) flash chip. The static state of a hardware signal could be a signal output from a hardware logic circuit on the baseboard. However, if the variety of required servers increase, it becomes a complicated task to create a sufficient variety of combination firmware image files, and change the output of hardware logic circuits for a production line. Further, silicon based hardware devices can only recognize a single section of configuration parameters, such as those of the Intel Platform Controller Hub (PCH). Since configuration parameters of a PCH reside in a specific region of the combination firmware image file, a firmware designer must rebuild the combination firmware image file if either a specific function is activated or deactivated, or a configuration parameter of PCH is changed.
In general, the silicon vendor usually provides multiple functions inside its chipset and allows a developer to select and deploy functions with an associated hardware circuit on a server baseboard. The developer may decide what functions inside the chipset are active or inactive during the power on sequence of the baseboard. Once the functions are selected, the output pins of the chipset may go through an internal multiplexer and data selector to connect with an external hardware circuit. The chipset usually provides several mechanisms to identify what function should be active or inactive, such as those of the Intel Platform Controller Hub (PCH). Configuration parameters of the PCH reside in a specific region of the combination firmware image file. Such configuration parameters are termed “software straps.”
FIG. 1 shows a conventional process for selection of software straps. FIG. 1 includes a platform controller hub (PCH) chip 10. The PCH chip 10 has an internal SATA controller and an internal PCI root controller. The PCH chip 10 includes configuration parameter outputs 12 that may send parameter signals that are routed by either the internal SATA controller or internal PCI root controller. The parameter signals of the PCH chip 10 ultimately output configuration information for either a PCIe bus 14 or a SATA bus 16 depending on which controller is enabled. The parameters are termed software strap. The PCH 10 includes a SPI interface 18 that is coupled to a Serial Peripheral Interface (SPI) flash chip 20.
FIG. 1 shows a memory map 30 of a firmware image that is burned into the SPI flash chip 20. The memory map 30 includes a reserved region 32, a PCH software strap region 34, a reserved region 36, a BIOS region 38, a descriptor map region 40, and a signature region 42. The PCH software strap region 34 is shown as a table 50 that includes a bit location and the description of the bit fields and represents a software strap. In this example, the software strap in the table 50 includes selections for values for the parameter outputs 12 of the PCH chip 10. Thus, the table 50 is an example of parameters showing how the platform controller hub chip 10 routes one of the two internal controllers (sSATA or PCIe) to a single port output. It is similar to a multiplexer when selecting either one of the controllers to provide the output signal for enabling functions from either the internal PCI root controller or internal SATA controller to the respective PCIe bus 14 or SATA bus 16.
The resulting outputs of the parameter outputs 12 of the PCH 10 are shown in a table 52. As shown in table 52, the first two ports of the parameter outputs 12 are fixed signals. The third and fourth ports of the parameter outputs 12 may be multiplexed. The table 52 is an example of PCH silicon design. The two different controllers (sSATA & PCIe) are present in the platform controller hub chip 10, but the platform controller hub only provides a single port output that allows selection of either controller for connection. Only a multiplexed signal may provide an output port selection as opposed to a fixed signal that does not provide an output port selection option.
Similarly, FIG. 2 shows a conventional configuration process of hardware settings for a processor that are termed “hardware straps.” In this process, a processor 60 such as an Intel processor, includes input pins that define different functions that may be performed by the processor 60. The feature configuration of the processor 60 depends on the static state of a hardware input signal from a logic circuit 62 having hardware registers, that are connected to input pins 64. The logic circuit 62 is mounted on the baseboard of the server according to the customer bill of material in this example. A table 66 may include the static states constituting the hardware straps that configure the function of the processor 60. In this example, the functions of the processor 60 are determined by the state of the signals connected to the input pins 64 during the power on sequence.
Since the software straps and hardware straps shown in FIGS. 1 and 2 are static parameters and fixed states, modifying them may need extra coding, compiling, releasing, and strict processing of maintenance and after service if a variety of different function baseboards are desired. Such a process results in extended costs for maintenance of different revisions of a firmware image file for customer. Further, it requires a complicated process to modify the hardware logic circuit of a baseboard production line should new server designs with different functions be required.
Thus, there a need for a streamlined process to allow production of different servers with different functions. There is a further need for flexible configuration to allow different server functions without modifying hardware logic circuits or rewriting firmware images.